LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY TEST_MEM_UNIT IS
END TEST_MEM_UNIT;
 
ARCHITECTURE behavior OF TEST_MEM_UNIT IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT MEM_UNIT
    PORT(
         CLK : IN  std_logic;
         BRANCH_IN : IN  std_logic;
         MEM_READ_IN : IN  std_logic;
         MEM_WRITE_IN : IN  std_logic;
         BRANCH_FLAG_IN : IN  std_logic;
         REG_WRITE_IN : IN  std_logic;
         MEM_TO_REG_IN : IN  std_logic;
         ALU_IN : IN  std_logic_vector(31 downto 0);
         WRITE_DATA : IN  std_logic_vector(31 downto 0);
         REG_DEST_IN : IN  std_logic_vector(4 downto 0);
         PC_SRC : OUT  std_logic;
         REG_WRITE_OUT : OUT  std_logic;
         MEM_TO_REG_OUT : OUT  std_logic;
         ALU_OUT : OUT  std_logic_vector(31 downto 0);
         MEMORY_OUT : OUT  std_logic_vector(31 downto 0);
         REG_DEST_OUT : OUT  std_logic_vector(4 downto 0);
         U_RES1_OUT : OUT  std_logic_vector(31 downto 0);
         U_RES2_OUT : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal CLK : std_logic := '0';
   signal BRANCH_IN : std_logic := '0';
   signal MEM_READ_IN : std_logic := '0';
   signal MEM_WRITE_IN : std_logic := '0';
   signal BRANCH_FLAG_IN : std_logic := '0';
   signal REG_WRITE_IN : std_logic := '0';
   signal MEM_TO_REG_IN : std_logic := '0';
   signal ALU_IN : std_logic_vector(31 downto 0) := (others => '0');
   signal WRITE_DATA : std_logic_vector(31 downto 0) := (others => '0');
   signal REG_DEST_IN : std_logic_vector(4 downto 0) := (others => '0');

 	--Outputs
   signal PC_SRC : std_logic;
   signal REG_WRITE_OUT : std_logic;
   signal MEM_TO_REG_OUT : std_logic;
   signal ALU_OUT : std_logic_vector(31 downto 0);
   signal MEMORY_OUT : std_logic_vector(31 downto 0);
   signal REG_DEST_OUT : std_logic_vector(4 downto 0);
   signal U_RES1_OUT : std_logic_vector(31 downto 0);
   signal U_RES2_OUT : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant CLK_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: MEM_UNIT PORT MAP (
          CLK => CLK,
          BRANCH_IN => BRANCH_IN,
          MEM_READ_IN => MEM_READ_IN,
          MEM_WRITE_IN => MEM_WRITE_IN,
          BRANCH_FLAG_IN => BRANCH_FLAG_IN,
          REG_WRITE_IN => REG_WRITE_IN,
          MEM_TO_REG_IN => MEM_TO_REG_IN,
          ALU_IN => ALU_IN,
          WRITE_DATA => WRITE_DATA,
          REG_DEST_IN => REG_DEST_IN,
          PC_SRC => PC_SRC,
          REG_WRITE_OUT => REG_WRITE_OUT,
          MEM_TO_REG_OUT => MEM_TO_REG_OUT,
          ALU_OUT => ALU_OUT,
          MEMORY_OUT => MEMORY_OUT,
          REG_DEST_OUT => REG_DEST_OUT,
          U_RES1_OUT => U_RES1_OUT,
          U_RES2_OUT => U_RES2_OUT
        );

   -- Clock process definitions
   CLK_process :process
   begin
		CLK <= '0';
		wait for CLK_period/2;
		CLK <= '1';
		wait for CLK_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for CLK_period*10;
		
      -- insert stimulus here 
		-- test output to I/O
      BRANCH_IN <= '0';
      MEM_READ_IN <= '0';
      MEM_WRITE_IN <= '1';
      BRANCH_FLAG_IN <= '0';
      REG_WRITE_IN <= '0';
      MEM_TO_REG_IN <= '0';
      ALU_IN <= x"00000002"; -- write to res1
      WRITE_DATA <= x"87654321";
      REG_DEST_IN <= "11111";

      wait;
   end process;

END;
